SOI-CMOS Device Technology

In recent years, the mobile communication market represented by the mobile telephone has been showing remarkable growth. This market has been making tough demands for semiconductor integrated circuits, which are mounted components, to consume less power, have higher integration, have multi-function capability, and be faster. We at Oki have been working on developing complete depletion type SOI devices in order to meet these needs. We have already implemented 0.35 m and 0.2 m SOI-CMOS devices. This article explains SOI-CMOS device technology and discusses current developments. * Silicon Solutions Company, VLSI R&D Center, Advanced VLSI Device/Process R&D Dept.-1, General Manager ** Silicon Solutions Company, VLSI R&D Center, AdvancedVLSI Device/Process R&D Dept.-1, SOI Circuit R&D Team-2, Team Leader SOI Device Structure The term SOI means Silicon On Insulator structure, which consists of devices on silicon thin film (SOI layers) that exists on insulating film. Figure 1 illustrates an outline sketch of bulk, partial depletion type and complete depletion type SOI-MOS (Metal Oxide Semiconductor) transistor structure. In the case of bulk CMOS devices, P/N type MOS transistors are isolated from the well layer. In contrast, SOI-CMOS devices are separated into Si supporting substrate and buried oxide film (BOX). Also, these devices are structured so each element is completely isolated by LOCOS (Local Oxidation of Silicon) oxide film and the operating elements area (called the SOI layer) is completely isolated by insulators. Also, elements that have a thin SOI layer (normally <50 nm) and have all body areas under the channel depleted, are called complete depletion type SOI. Conversely, elements that have a thick SOI layer (normally >100 nm) and have some areas at the bottom of the body area that are not depleted, are called partial depletion type SOI. Characteristics of SOI-CMOS Devices As indicated below in Table 1, the S value that indicates the sub-threshold characteristics is unique in that only the S value of complete depletion type SOI transistors is the low value of 60 70 mV/dec. (The S value is the gate voltage at the sub-threshold area that changes the drain current by one digit with the drain voltage held constant.) Also, as illustrated in Figure 1, the source, drain, substrate, and the PN junction formed between wells in bulk transistors do not exist as complete depletion type transistors. Also, the junction capacity is very small. Since a PN junction exists at the bottom of the body in partial depletion type transistors, it is located exactly between them. The advantages of the S value, reduced junction capacitance, and the totally isolated structure are as follows. 1. A low operating voltage is possible since the threshold voltage (Vt) can be set low without increasing the offleak current. (Reduced S value) 2. Development of high-speed, low power consumption CMOS devices is possible since the load capacitance CL is reduced. (Reduced junction capacitance) 3. Reduced signal transmission loss during high-speed operation. (Reduced junction capacitance) 4. Realizing high-frequency component performance, including passive devices, is possible since high-resistance Si wafers can be used as supporting substrates. (Totally isolated structure) 5. Reduced operation errors such as cross talk via the substrate. (Totally isolated structure) 6. It is possible to prevent operation errors including latch up phenomena. (Totally isolated structure)